ANALOG DESIGN AND LAYOUT
Analog and mixed signal functional blocks and IPs: Pre-amplifier, buffer, Op Amp, Comparator, PLL, ADC, DAC, clock and timing circuits and power management such as LDO regulator
I/O interfaces: MIPI, LVDS, SerDes, DDRPhy and such serial and parallel data interfaces
RF functional blocks such as amplifiers, buffers, oscillators, Bandgap and phase locked loops
Physical verification and full chip integration
Development experience spans across popular EDA tools from Cadence, Synopsys, and Mentor Graphics
PHYSICAL DESIGN
Floor planning, power planning and IO planning
DRC/ LVS testing and verification
Performance analysis such as power, signal integrity, and IR
Die area estimation of macros/IOs and estimation based on pads and logic block area
Full chip design with packaging-part and closure
Design partition and hardening
Signoff Timing Closure
Low power design implementation
Physical Verification
Static Timing Analysis (STA)
Deep node FinFET technologies
RTL AND VERIFICATION
RTL Coding, Simulation.
Test bench development.
Verification IP development.
Understanding product requirements and specifications.
Developing Micro Architecture Document and HLD.
Automation at both module and system level to reduce manual effort.
Mixed-mode verification using C/C++, Verilog/VHDL, assembly and assertions.
System verilog, UVM Methodologies.
Help in understanding and RTL Implementation of DFT.
EMBEDDED SYSTEMS
Embedded software development
Device Driver, BSP, PDK and reference designs
IOT product development
Linux and Real Time OS development
Embedded board design
User Interface